kc3-lang/libjpeg-turbo/simd/x86_64/jsimdcpu.asm

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• Hash : aa9db616
  Author :
  Date : 2019-04-15T17:55:47
  

  x86 SIMD: Check for CPUID leaf 07H before using
  
  According to Intel's manual [1], "If a value entered for CPUID.EAX is
  higher than the maximum input value for basic or extended function for
  that processor then the data for the highest basic information leaf is
  returned."
  
  Right now, libjpeg-turbo doesn't first check that leaf 07H is supported
  before attempting to use it, so the ostensible AVX2 bit (Bit 05) of the
  CPUID result might actually be Bit 05 from a lower leaf.  That bit might
  be set, even if the CPU doesn't support AVX2.
  
  This commit modifies the x86 and x86-64 SIMD feature detection code so
  that it first checks whether CPUID leaf 07H is supported before
  attempting to use it to check for AVX2 instruction support.
  
  DRC:
  This commit should fix
  https://bugzilla.mozilla.org/show_bug.cgi?id=1520760
  However, I have not personally been able to reproduce that issue,
  despite using a Nehalem (pre-AVX2) CPU on which the maximum CPUID leaf
  has been limited via a BIOS setting.
  
  Closes #348
  
  [1]
  "Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (2A, 2B, 2C & 2D): Instruction Set Reference, A-Z", https://software.intel.com/sites/default/files/managed/a4/60/325383-sdm-vol-2abcd.pdf, page 3-192.
  

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• simd/x86_64/jsimdcpu.asm

• ;
  ; jsimdcpu.asm - SIMD instruction support check
  ;
  ; Copyright 2009 Pierre Ossman <ossman@cendio.se> for Cendio AB
  ; Copyright (C) 2016, D. R. Commander.
  ;
  ; Based on
  ; x86 SIMD extension for IJG JPEG library
  ; Copyright (C) 1999-2006, MIYASAKA Masaru.
  ; For conditions of distribution and use, see copyright notice in jsimdext.inc
  ;
  ; This file should be assembled with NASM (Netwide Assembler),
  ; can *not* be assembled with Microsoft's MASM or any compatible
  ; assembler (including Borland's Turbo Assembler).
  ; NASM is available from http://nasm.sourceforge.net/ or
  ; http://sourceforge.net/project/showfiles.php?group_id=6208
  ;
  ; [TAB8]
  
  %include "jsimdext.inc"
  
  ; --------------------------------------------------------------------------
      SECTION     SEG_TEXT
      BITS        64
  ;
  ; Check if the CPU supports SIMD instructions
  ;
  ; GLOBAL(unsigned int)
  ; jpeg_simd_cpu_support(void)
  ;
  
      align       32
      GLOBAL_FUNCTION(jpeg_simd_cpu_support)
  
  EXTN(jpeg_simd_cpu_support):
      push        rbx
      push        rdi
  
      xor         rdi, rdi                ; simd support flag
  
      ; Assume that all x86-64 processors support SSE & SSE2 instructions
      or          rdi, JSIMD_SSE2
      or          rdi, JSIMD_SSE
  
      ; Check whether CPUID leaf 07H is supported
      ; (leaf 07H is used to check for AVX2 instruction support)
      mov         rax, 0
      cpuid
      cmp         rax, 7
      jl          short .return           ; Maximum leaf < 07H
  
      ; Check for AVX2 instruction support
      mov         rax, 7
      xor         rcx, rcx
      cpuid
      mov         rax, rbx                ; rax = Extended feature flags
  
      test        rax, 1<<5               ; bit5:AVX2
      jz          short .return
  
      ; Check for AVX2 O/S support
      mov         rax, 1
      xor         rcx, rcx
      cpuid
      test        rcx, 1<<27
      jz          short .return           ; O/S does not support XSAVE
      test        rcx, 1<<28
      jz          short .return           ; CPU does not support AVX2
  
      xor         rcx, rcx
      xgetbv
      and         rax, 6
      cmp         rax, 6                  ; O/S does not manage XMM/YMM state
                                          ; using XSAVE
      jnz         short .return
  
      or          rdi, JSIMD_AVX2
  
  .return:
      mov         rax, rdi
  
      pop         rdi
      pop         rbx
      ret
  
  ; For some reason, the OS X linker does not honor the request to align the
  ; segment unless we do this.
      align       32
  

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