IABSD.fr/ports/emulators/spike
Branch :
Log
| Author | Commit | Date | CI | Message |
|---|---|---|---|---|
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160803cb | 2026-02-10 13:25:01 | Mechanical WANTLIB sync after Boost update | |
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0a8315ca | 2024-02-07 20:26:22 | update to spike-1.1.0 | |
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06ebc532 | 2022-03-11 18:59:33 | drop RCS Ids | |
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009d64ee | 2021-10-27 13:03:59 | Fix build on riscv64 ok jasper@ (maintainer) | |
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62dd7a11 | 2020-12-01 21:54:58 | spike: big endian and base-gcc architectures fixes - big endian archs: correct a type mismatch in a template function call, that caused a build failure. - base-gcc archs: Add a COMPILER line since it requires ports-gcc (C++11). - powerpc: The simulation generates internal exceptions, mark it BROKEN. OK kmos@ (who tested on sparc64, thanks!) and jasper@ (maintainer) | |
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b64e1145 | 2020-11-05 08:35:16 | compile disasm files with -O1 to half memory usage (to 4GB) when compiling these files | |
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da693dd6 | 2020-11-04 14:40:03 | disable spike on i386, compiling disasm.cc uses more memory than there is available address space. | |
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1e0c75e9 | 2020-11-01 15:01:37 | import spike (git HEAD) Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V harts. ok aja@ |