IABSD.fr/ports/cad/opensta/pkg

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Log

Author Commit Date CI Message
5bba7c30 2022-03-11 18:24:26 drop RCS Ids
cf4db000 2020-09-25 19:00:10 update to OpenSTA-2.2.0, from maintainer Alessandro De Laurenzis
d359e50c 2020-03-14 06:42:05 Update opensta to 2.0.18.20200308 "This is a trivial update port-wise, but a big jump in terms of features/bug-fixing." Notable port changes: - updated maintainer email address; - ApiChanges.txt added to ${PREFIX}/share/doc/opensta; - new enabled regression suite Diff from maintainer Alessandro De Laurenzis
80391237 2019-03-30 11:50:06 Update to opensta-2.0.12.20190329. Adds a missing header file used by dependent projects. From Alessandro De Laurenzis (maintainer); thanks!
96c8a0f2 2019-03-27 08:45:25 Import opensta-2.0.11.20190327. OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats: - Verilog netlist - Liberty library - SDC timing constraints - SDF delay annotation - SPEF parasitics From Alessandro De Laurenzis; thanks! ok sthen@