kmx.io/prism.js

diff --git a/components.js b/components.js
index 53ff134..3140fd4 100644
--- a/components.js
+++ b/components.js
@@ -328,10 +328,6 @@ var components = {
 			"require": "clike",
 			"owner": "chrischares"
 		},
-		"system_verilog": {
-			"title": "System Verilog",
-			"owner": "a-rey"
-		},
 		"twig": {
 			"title": "Twig",
 			"require": "markup",
@@ -342,6 +338,10 @@ var components = {
 			"require": "javascript",
 			"owner": "vkbansal"
 		},
+		"verilog": {
+			"title": "Verilog & System Verilog",
+			"owner": "a-rey"
+		},
 		"vhdl": {
 			"title": "VHDL",
 			"owner": "a-rey"
diff --git a/components/prism-system_verilog.js b/components/prism-system_verilog.js
deleted file mode 100644
index 99a0cbf..0000000
--- a/components/prism-system_verilog.js
+++ /dev/null
@@ -1,23 +0,0 @@
-Prism.languages.system_verilog = {
-  'comment': /\/\/.*|\/\*[\w\W]*?\*\//,
-  'string': /"(\\\n|\\?.)*?"/,
-  // support for any kernel function (ex: $display())
-  'property': /(?!\b)\$\w+\b/,
-  // support for user defined constants (ex: `define)
-  'constant': /(?!\b)`\w+\b/,
-  'function': {
-    'pattern': /[a-z0-9_]+\(/i,
-    'inside': {
-      'punctuation': /\(/
-    }
-  },
-  'boolean': /\b(true|false)\b/i,
-  // support for verilog and system verilog keywords
-  'keyword': /\b(alias|and|assert|assign|assume|automatic|before|begin|bind|bins|binsof|bit|break|buf|bufif0|bufif1|byte|class|case|casex|casez|cell|chandle|clocking|cmos|config|const|constraint|context|continue|cover|covergroup|coverpoint|cross|deassign|default|defparam|design|disable|dist|do|edge|else|end|endcase|endclass|endclocking|endconfig|endfunction|endgenerate|endgroup|endinterface|endmodule|endpackage|endprimitive|endprogram|endproperty|endspecify|endsequence|endtable|endtask|enum|event|expect|export|extends|extern|final|first_match|for|force|foreach|forever|fork|forkjoin|function|generate|genvar|highz0|highz1|if|iff|ifnone|ignore_bins|illegal_bins|import|incdir|include|initial|inout|input|inside|instance|int|integer|interface|intersect|join|join_any|join_none|large|liblist|library|local|localparam|logic|longint|macromodule|matches|medium|modport|module|nand|negedge|new|nmos|nor|noshowcancelled|not|notif0|notif1|null|or|output|package|packed|parameter|pmos|posedge|primitive|priority|program|property|protected|pull0|pull1|pulldown|pullup|pulsestyle_onevent|pulsestyle_ondetect|pure|rand|randc|randcase|randsequence|rcmos|real|realtime|ref|reg|release|repeat|return|rnmos|rpmos|rtran|rtranif0|rtranif1|scalared|sequence|shortint|shortreal|showcancelled|signed|small|solve|specify|specparam|static|string|strong0|strong1|struct|super|supply0|supply1|table|tagged|task|this|throughout|time|timeprecision|timeunit|tran|tranif0|tranif1|tri|tri0|tri1|triand|trior|trireg|type|typedef|union|unique|unsigned|use|uwire|var|vectored|virtual|void|wait|wait_order|wand|weak0|weak1|while|wildcard|wire|with|within|wor|xnor|xor)\b/,
-  // bold highlighting for all verilog and system verilog logic blocks
-  'important': /\b(always_latch|always_comb|always_ff|always) ?@?/,
-  // support for time ticks, vectors, and real numbers
-  'number': /(?!\b)#{1,2}\d+|(\b\d+)?'[odbh] ?[\da-f10zx_\?]+|\b\d+[._]?(e-?\d+)?/i,
-  'operator': /[-+\{\}]|!=?|<{1,2}=?|>{1,2}=?|={1,3}|\^|~|%|&{1,2}|\|?\||\?|\*|\//,
-  'punctuation': /[[\];(),.:]/,
-};
\ No newline at end of file
diff --git a/components/prism-system_verilog.min.js b/components/prism-system_verilog.min.js
deleted file mode 100644
index 60470bc..0000000
--- a/components/prism-system_verilog.min.js
+++ /dev/null
@@ -1 +0,0 @@
-Prism.languages.system_verilog={comment:/\/\/.*|\/\*[\w\W]*?\*\//,string:/"(\\\n|\\?.)*?"/,property:/(?!\b)\$\w+\b/,constant:/(?!\b)`\w+\b/,"function":{pattern:/[a-z0-9_]+\(/i,inside:{punctuation:/\(/}},"boolean":/\b(true|false)\b/i,keyword:/\b(alias|and|assert|assign|assume|automatic|before|begin|bind|bins|binsof|bit|break|buf|bufif0|bufif1|byte|class|case|casex|casez|cell|chandle|clocking|cmos|config|const|constraint|context|continue|cover|covergroup|coverpoint|cross|deassign|default|defparam|design|disable|dist|do|edge|else|end|endcase|endclass|endclocking|endconfig|endfunction|endgenerate|endgroup|endinterface|endmodule|endpackage|endprimitive|endprogram|endproperty|endspecify|endsequence|endtable|endtask|enum|event|expect|export|extends|extern|final|first_match|for|force|foreach|forever|fork|forkjoin|function|generate|genvar|highz0|highz1|if|iff|ifnone|ignore_bins|illegal_bins|import|incdir|include|initial|inout|input|inside|instance|int|integer|interface|intersect|join|join_any|join_none|large|liblist|library|local|localparam|logic|longint|macromodule|matches|medium|modport|module|nand|negedge|new|nmos|nor|noshowcancelled|not|notif0|notif1|null|or|output|package|packed|parameter|pmos|posedge|primitive|priority|program|property|protected|pull0|pull1|pulldown|pullup|pulsestyle_onevent|pulsestyle_ondetect|pure|rand|randc|randcase|randsequence|rcmos|real|realtime|ref|reg|release|repeat|return|rnmos|rpmos|rtran|rtranif0|rtranif1|scalared|sequence|shortint|shortreal|showcancelled|signed|small|solve|specify|specparam|static|string|strong0|strong1|struct|super|supply0|supply1|table|tagged|task|this|throughout|time|timeprecision|timeunit|tran|tranif0|tranif1|tri|tri0|tri1|triand|trior|trireg|type|typedef|union|unique|unsigned|use|uwire|var|vectored|virtual|void|wait|wait_order|wand|weak0|weak1|while|wildcard|wire|with|within|wor|xnor|xor)\b/,important:/\b(always_latch|always_comb|always_ff|always) ?@?/,number:/(?!\b)#{1,2}\d+|(\b\d+)?'[odbh] ?[\da-f10zx_\?]+|\b\d+[._]?(e-?\d+)?/i,operator:/[-+\{\}]|!=?|<{1,2}=?|>{1,2}=?|={1,3}|\^|~|%|&{1,2}|\|?\||\?|\*|\//,punctuation:/[[\];(),.:]/};
\ No newline at end of file
diff --git a/components/prism-verilog.js b/components/prism-verilog.js
new file mode 100644
index 0000000..868b886
--- /dev/null
+++ b/components/prism-verilog.js
@@ -0,0 +1,17 @@
+Prism.languages.verilog = {
+  'comment': /\/\/.*|\/\*[\w\W]*?\*\//,
+  'string': /"(\\(?:\r\n?|\n)|\\?.)*?"/,
+  // support for any kernel function (ex: $display())
+  'property': /\B\$\w+\b/,
+  // support for user defined constants (ex: `define)
+  'constant': /\B`\w+\b/,
+  'function': /[a-z\d_]+(?=\()/i,
+  // support for verilog and system verilog keywords
+  'keyword': /\b(alias|and|assert|assign|assume|automatic|before|begin|bind|bins|binsof|bit|break|buf|bufif0|bufif1|byte|class|case|casex|casez|cell|chandle|clocking|cmos|config|const|constraint|context|continue|cover|covergroup|coverpoint|cross|deassign|default|defparam|design|disable|dist|do|edge|else|end|endcase|endclass|endclocking|endconfig|endfunction|endgenerate|endgroup|endinterface|endmodule|endpackage|endprimitive|endprogram|endproperty|endspecify|endsequence|endtable|endtask|enum|event|expect|export|extends|extern|final|first_match|for|force|foreach|forever|fork|forkjoin|function|generate|genvar|highz0|highz1|if|iff|ifnone|ignore_bins|illegal_bins|import|incdir|include|initial|inout|input|inside|instance|int|integer|interface|intersect|join|join_any|join_none|large|liblist|library|local|localparam|logic|longint|macromodule|matches|medium|modport|module|nand|negedge|new|nmos|nor|noshowcancelled|not|notif0|notif1|null|or|output|package|packed|parameter|pmos|posedge|primitive|priority|program|property|protected|pull0|pull1|pulldown|pullup|pulsestyle_onevent|pulsestyle_ondetect|pure|rand|randc|randcase|randsequence|rcmos|real|realtime|ref|reg|release|repeat|return|rnmos|rpmos|rtran|rtranif0|rtranif1|scalared|sequence|shortint|shortreal|showcancelled|signed|small|solve|specify|specparam|static|string|strong0|strong1|struct|super|supply0|supply1|table|tagged|task|this|throughout|time|timeprecision|timeunit|tran|tranif0|tranif1|tri|tri0|tri1|triand|trior|trireg|type|typedef|union|unique|unsigned|use|uwire|var|vectored|virtual|void|wait|wait_order|wand|weak0|weak1|while|wildcard|wire|with|within|wor|xnor|xor)\b/,
+  // bold highlighting for all verilog and system verilog logic blocks
+  'important': /\b(always_latch|always_comb|always_ff|always) ?@?/,
+  // support for time ticks, vectors, and real numbers
+  'number': /\B##?\d+|(\b\d+)?'[odbh] ?[\da-fzx_?]+|\b\d*[._]?\d+(e[-+]?\d+)?/i,
+  'operator': /[-+{}^~%*\/?=!<>&|]+/,
+  'punctuation': /[[\];(),.:]/,
+};
\ No newline at end of file
diff --git a/components/prism-verilog.min.js b/components/prism-verilog.min.js
new file mode 100644
index 0000000..bb11cc5
--- /dev/null
+++ b/components/prism-verilog.min.js
@@ -0,0 +1 @@
+Prism.languages.verilog={comment:/\/\/.*|\/\*[\w\W]*?\*\//,string:/"(\\(?:\r\n?|\n)|\\?.)*?"/,property:/\B\$\w+\b/,constant:/\B`\w+\b/,"function":/[a-z\d_]+(?=\()/i,keyword:/\b(alias|and|assert|assign|assume|automatic|before|begin|bind|bins|binsof|bit|break|buf|bufif0|bufif1|byte|class|case|casex|casez|cell|chandle|clocking|cmos|config|const|constraint|context|continue|cover|covergroup|coverpoint|cross|deassign|default|defparam|design|disable|dist|do|edge|else|end|endcase|endclass|endclocking|endconfig|endfunction|endgenerate|endgroup|endinterface|endmodule|endpackage|endprimitive|endprogram|endproperty|endspecify|endsequence|endtable|endtask|enum|event|expect|export|extends|extern|final|first_match|for|force|foreach|forever|fork|forkjoin|function|generate|genvar|highz0|highz1|if|iff|ifnone|ignore_bins|illegal_bins|import|incdir|include|initial|inout|input|inside|instance|int|integer|interface|intersect|join|join_any|join_none|large|liblist|library|local|localparam|logic|longint|macromodule|matches|medium|modport|module|nand|negedge|new|nmos|nor|noshowcancelled|not|notif0|notif1|null|or|output|package|packed|parameter|pmos|posedge|primitive|priority|program|property|protected|pull0|pull1|pulldown|pullup|pulsestyle_onevent|pulsestyle_ondetect|pure|rand|randc|randcase|randsequence|rcmos|real|realtime|ref|reg|release|repeat|return|rnmos|rpmos|rtran|rtranif0|rtranif1|scalared|sequence|shortint|shortreal|showcancelled|signed|small|solve|specify|specparam|static|string|strong0|strong1|struct|super|supply0|supply1|table|tagged|task|this|throughout|time|timeprecision|timeunit|tran|tranif0|tranif1|tri|tri0|tri1|triand|trior|trireg|type|typedef|union|unique|unsigned|use|uwire|var|vectored|virtual|void|wait|wait_order|wand|weak0|weak1|while|wildcard|wire|with|within|wor|xnor|xor)\b/,important:/\b(always_latch|always_comb|always_ff|always) ?@?/,number:/\B##?\d+|(\b\d+)?'[odbh] ?[\da-fzx_?]+|\b\d*[._]?\d+(e[-+]?\d+)?/i,operator:/[-+{}^~%*\/?=!<>&|]+/,punctuation:/[[\];(),.:]/};
\ No newline at end of file
diff --git a/examples/prism-system_verilog.html b/examples/prism-system_verilog.html
deleted file mode 100644
index 2bbd840..0000000
--- a/examples/prism-system_verilog.html
+++ /dev/null
@@ -1,104 +0,0 @@
-<h1>System Verilog</h1>
-<p>To use this language, use the class "language-system_verilog".</p>
-
-<h2>Comments</h2>
-<pre><code>/* Multiline comments in Verilog
-   look like C comments and // is OK in here. */
-// Single-line comment in Verilog.</code></pre>
-
-<h2>Literals</h2>
-<pre><code>// example code from: http://iroi.seu.edu.cn/books/asics/Book2/CH11/CH11.02.htm
-module declarations;
-  parameter H12_UNSIZED = 'h 12;
-  parameter H12_SIZED = 6'h 12;
-  parameter D42 = 8'B0010_1010;
-  parameter D123 = 123;
-  parameter D63 = 8'o 77;
-  parameter A = 'h x, B = 'o x, C = 8'b x, D = 'h z, E = 16'h ????;
-  reg [3:0] B0011,Bxxx1,Bzzz1;
-  real R1,R2,R3;
-  integer I1,I3,I_3;
-  parameter BXZ = 8'b1x0x1z0z;
-
-  initial begin
-    B0011 = 4'b11; Bxxx1 = 4'bx1; Bzzz1 = 4'bz1;
-    R1 = 0.1e1; R2 = 2.0; R3 = 30E-01;
-    I1 = 1.1; I3 = 2.5; I_3 = -2.5;
-  end
-
-  initial begin #1;
-    $display("H12_UNSIZED, H12_SIZED (hex) = %h, %h",H12_UNSIZED, H12_SIZED);
-    $display("D42 (bin) = %b",D42," (dec) = %d",D42);
-    $display("D123 (hex) = %h",D123," (dec) = %d",D123);
-    $display("D63 (oct) = %o",D63);
-    $display("A (hex) = %h",A," B (hex) = %h",B);
-    $display("C (hex) = %h",C," D (hex) = %h",D," E (hex) = %h",E);
-    $display("BXZ (bin) = %b",BXZ," (hex) = %h",BXZ);
-    $display("B0011, Bxxx1, Bzzz1 (bin) = %b, %b, %b",B0011,Bxxx1,Bzzz1);
-    $display("R1, R2, R3 (e, f, g) = %e, %f, %g", R1, R2, R3);
-    $display("I1, I3, I_3 (d) = %d, %d, %d", I1, I3, I_3);
-  end
-endmodule</code></pre>
-
-<h2>Full example</h2>
-<pre><code>`include "internal_defines.vh"
-
-//*****************************************************************************
-// memory_decoder: a custom module used to handle memory transactions
-//*****************************************************************************
-//
-// out_mem (output) - The output to memory
-// out_reg (output) - The output to the register file
-// mem_we  (output) - Which byte in the word to write too
-// mem_in  (input)  - The input from memory
-// addr_in (input)  - The lowest 2 bits of byte offset to store in memory
-// data_in (input)  - The input from the register file to be stored
-// l_bit   (input)  - The load bit signal (control)
-// b_bit   (input)  - The byte bit signal (control)
-//
-module memory_decoder(out_mem, out_reg, mem_in, data_in, l_bit, b_bit, addr_in,
-                      mem_we);
-
-  output reg  [31:0]  out_mem, out_reg;
-  output reg  [3:0]   mem_we;
-  input       [31:0]  mem_in, data_in;
-  input       [1:0]   addr_in;
-  input               l_bit, b_bit;
-
-  always_comb begin
-    mem_we = 4'b0000;     // dont write memory by default
-    if (l_bit == 1) begin // ldr and ldrb
-      out_mem = mem_in;   // dont change memory!
-      if (b_bit == 1) begin
-        /* figure out which byte to load from memory */
-        case (addr_in)
-          2'b00: out_reg = {24'b00, mem_in[7:0]};
-          2'b01: out_reg = {24'b00, mem_in[15:8]};
-          2'b10: out_reg = {24'b00, mem_in[23:16]};
-          2'b11: out_reg = {24'b00, mem_in[31:24]};
-        endcase
-      end
-      else begin
-        out_reg = mem_in;
-      end
-    end
-    else begin            // str and strb
-      out_reg = `UNKNOWN; // We are not reading from mem
-      if (b_bit == 1) begin
-        /* figure out which byte to write to in memory */
-        out_mem = {4{data_in[7:0]}};
-        case (addr_in)
-          2'b00: mem_we = 4'b1000;
-          2'b01: mem_we = 4'b0100;
-          2'b10: mem_we = 4'b0010;
-          2'b11: mem_we = 4'b0001;
-        endcase
-      end
-      else begin
-        mem_we = 4'b1111; // write to all channels
-        out_mem = data_in;
-      end
-    end
-  end
-
-endmodule</code></pre>
\ No newline at end of file
diff --git a/examples/prism-verilog.html b/examples/prism-verilog.html
new file mode 100644
index 0000000..315d385
--- /dev/null
+++ b/examples/prism-verilog.html
@@ -0,0 +1,104 @@
+<h1>Verilog &amp; System Verilog</h1>
+<p>To use this language, use the class "language-verilog". Note that this package supports syntax highlighting for both Verilog and System Verilog.</p>
+
+<h2>Comments</h2>
+<pre><code>/* Multiline comments in Verilog
+   look like C comments and // is OK in here. */
+// Single-line comment in Verilog.</code></pre>
+
+<h2>Literals</h2>
+<pre><code>// example code from: http://iroi.seu.edu.cn/books/asics/Book2/CH11/CH11.02.htm
+module declarations;
+  parameter H12_UNSIZED = 'h 12;
+  parameter H12_SIZED = 6'h 12;
+  parameter D42 = 8'B0010_1010;
+  parameter D123 = 123;
+  parameter D63 = 8'o 77;
+  parameter A = 'h x, B = 'o x, C = 8'b x, D = 'h z, E = 16'h ????;
+  reg [3:0] B0011,Bxxx1,Bzzz1;
+  real R1,R2,R3;
+  integer I1,I3,I_3;
+  parameter BXZ = 8'b1x0x1z0z;
+
+  initial begin
+    B0011 = 4'b11; Bxxx1 = 4'bx1; Bzzz1 = 4'bz1;
+    R1 = 0.1e1; R2 = 2.0; R3 = 30E-01;
+    I1 = 1.1; I3 = 2.5; I_3 = -2.5;
+  end
+
+  initial begin #1;
+    $display("H12_UNSIZED, H12_SIZED (hex) = %h, %h",H12_UNSIZED, H12_SIZED);
+    $display("D42 (bin) = %b",D42," (dec) = %d",D42);
+    $display("D123 (hex) = %h",D123," (dec) = %d",D123);
+    $display("D63 (oct) = %o",D63);
+    $display("A (hex) = %h",A," B (hex) = %h",B);
+    $display("C (hex) = %h",C," D (hex) = %h",D," E (hex) = %h",E);
+    $display("BXZ (bin) = %b",BXZ," (hex) = %h",BXZ);
+    $display("B0011, Bxxx1, Bzzz1 (bin) = %b, %b, %b",B0011,Bxxx1,Bzzz1);
+    $display("R1, R2, R3 (e, f, g) = %e, %f, %g", R1, R2, R3);
+    $display("I1, I3, I_3 (d) = %d, %d, %d", I1, I3, I_3);
+  end
+endmodule</code></pre>
+
+<h2>Full example</h2>
+<pre><code>`include "internal_defines.vh"
+
+//*****************************************************************************
+// memory_decoder: a custom module used to handle memory transactions
+//*****************************************************************************
+//
+// out_mem (output) - The output to memory
+// out_reg (output) - The output to the register file
+// mem_we  (output) - Which byte in the word to write too
+// mem_in  (input)  - The input from memory
+// addr_in (input)  - The lowest 2 bits of byte offset to store in memory
+// data_in (input)  - The input from the register file to be stored
+// l_bit   (input)  - The load bit signal (control)
+// b_bit   (input)  - The byte bit signal (control)
+//
+module memory_decoder(out_mem, out_reg, mem_in, data_in, l_bit, b_bit, addr_in,
+                      mem_we);
+
+  output reg  [31:0]  out_mem, out_reg;
+  output reg  [3:0]   mem_we;
+  input       [31:0]  mem_in, data_in;
+  input       [1:0]   addr_in;
+  input               l_bit, b_bit;
+
+  always_comb begin
+    mem_we = 4'b0000;     // dont write memory by default
+    if (l_bit == 1) begin // ldr and ldrb
+      out_mem = mem_in;   // dont change memory!
+      if (b_bit == 1) begin
+        /* figure out which byte to load from memory */
+        case (addr_in)
+          2'b00: out_reg = {24'b00, mem_in[7:0]};
+          2'b01: out_reg = {24'b00, mem_in[15:8]};
+          2'b10: out_reg = {24'b00, mem_in[23:16]};
+          2'b11: out_reg = {24'b00, mem_in[31:24]};
+        endcase
+      end
+      else begin
+        out_reg = mem_in;
+      end
+    end
+    else begin            // str and strb
+      out_reg = `UNKNOWN; // We are not reading from mem
+      if (b_bit == 1) begin
+        /* figure out which byte to write to in memory */
+        out_mem = {4{data_in[7:0]}};
+        case (addr_in)
+          2'b00: mem_we = 4'b1000;
+          2'b01: mem_we = 4'b0100;
+          2'b10: mem_we = 4'b0010;
+          2'b11: mem_we = 4'b0001;
+        endcase
+      end
+      else begin
+        mem_we = 4'b1111; // write to all channels
+        out_mem = data_in;
+      end
+    end
+  end
+
+endmodule</code></pre>
\ No newline at end of file