Commit 43e6157d3d534f66addc832ac1e317127e05f0b4
2015-06-18T18:52:55
Merge pull request #595 from a-rey/add-vhdl adding vhdl language
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154
diff --git a/components.js b/components.js
index 7523fae..a700572 100644
--- a/components.js
+++ b/components.js
@@ -326,6 +326,10 @@ var components = {
"require": "javascript",
"owner": "vkbansal"
},
+ "vhdl": {
+ "title": "VHDL",
+ "owner": "a-rey"
+ },
"wiki": {
"title": "Wiki markup",
"require": "markup",
diff --git a/components/prism-vhdl.js b/components/prism-vhdl.js
new file mode 100644
index 0000000..bed5ffe
--- /dev/null
+++ b/components/prism-vhdl.js
@@ -0,0 +1,24 @@
+Prism.languages.vhdl = {
+ 'comment': /--.+/,
+ // support for all logic vectors
+ 'vhdl-vectors': {
+ 'pattern': /\b[oxb]"[\da-f_]+"|"[01uxzwlh-]+"/i,
+ 'alias': 'number'
+ },
+ 'string': /"(\\\n|\\?.)*?"/,
+ 'constant': /\b(use|library)\b/i,
+ // support for predefined attributes included
+ 'keyword': /\b('active|'ascending|'base|'delayed|'driving|'driving_value|'event|'high|'image|'instance_name|'last_active|'last_event|'last_value|'left|'leftof|'length|'low|'path_name|'pos|'pred|'quiet|'range|'reverse_range|'right|'rightof|'simple_name|'stable|'succ|'transaction|'val|'value|access|after|alias|all|architecture|array|assert|attribute|begin|block|body|buffer|bus|case|component|configuration|constant|disconnect|downto|else|elsif|end|entity|exit|file|for|function|generate|generic|group|guarded|if|impure|in|inertial|inout|is|label|library|linkage|literal|loop|map|new|next|null|of|on|open|others|out|package|port|postponed|procedure|process|pure|range|record|register|reject|report|return|select|severity|shared|signal|subtype|then|to|transport|type|unaffected|units|until|use|variable|wait|when|while|with)\b/i,
+ 'boolean': /\b(true|false)\b/i,
+ 'function': {
+ // support for operator overloading included
+ pattern: /([a-z0-9_]+|"\S+")\(/i,
+ inside: {
+ punctuation: /\(/
+ }
+ },
+ // decimal, based, physical, and exponential numbers supported
+ 'number': /'[01uxzwlh-]'|\b\d+[_.]*(#[\da-f_.]+#)?(e[-+]?\d+)?/i,
+ 'operator': /<=?|>=?|:=|[-+*/&=]|\b(abs|not|mod|rem|sll|srl|sla|sra|rol|ror|and|or|nand|xnor|xor|nor)\b/i,
+ 'punctuation': /[{}[\];(),.:]/
+};
diff --git a/components/prism-vhdl.min.js b/components/prism-vhdl.min.js
new file mode 100644
index 0000000..3680f05
--- /dev/null
+++ b/components/prism-vhdl.min.js
@@ -0,0 +1 @@
+Prism.languages.vhdl={comment:/--.+/,"vhdl-vectors":{pattern:/\b[oxb]"[\da-f_]+"|"[01uxzwlh-]+"/i,alias:"number"},string:/"(\\\n|\\?.)*?"/,constant:/\b(use|library)\b/i,keyword:/\b('active|'ascending|'base|'delayed|'driving|'driving_value|'event|'high|'image|'instance_name|'last_active|'last_event|'last_value|'left|'leftof|'length|'low|'path_name|'pos|'pred|'quiet|'range|'reverse_range|'right|'rightof|'simple_name|'stable|'succ|'transaction|'val|'value|access|after|alias|all|architecture|array|assert|attribute|begin|block|body|buffer|bus|case|component|configuration|constant|disconnect|downto|else|elsif|end|entity|exit|file|for|function|generate|generic|group|guarded|if|impure|in|inertial|inout|is|label|library|linkage|literal|loop|map|new|next|null|of|on|open|others|out|package|port|postponed|procedure|process|pure|range|record|register|reject|report|return|select|severity|shared|signal|subtype|then|to|transport|type|unaffected|units|until|use|variable|wait|when|while|with)\b/i,"boolean":/\b(true|false)\b/i,"function":{pattern:/([a-z0-9_]+|"\S+")\(/i,inside:{punctuation:/\(/}},number:/'[01uxzwlh-]'|\b\d+[_.]*(#[\da-f_.]+#)?(e[-+]?\d+)?/i,operator:/<=?|>=?|:=|[-+*/&=]|\b(abs|not|mod|rem|sll|srl|sla|sra|rol|ror|and|or|nand|xnor|xor|nor)\b/i,punctuation:/[{}[\];(),.:]/};
\ No newline at end of file
diff --git a/examples/prism-vhdl.html b/examples/prism-vhdl.html
new file mode 100644
index 0000000..1dbf649
--- /dev/null
+++ b/examples/prism-vhdl.html
@@ -0,0 +1,95 @@
+<h1>VHDL</h1>
+<p>To use this language, use the class "language-vhdl".</p>
+
+<h2>Comments</h2>
+<pre><code>-- I am a comment
+I am not</code></pre>
+
+<h2>Literals</h2>
+<pre><code>constant FREEZE : integer := 32;
+constant TEMP : real := 32.0;
+A_INT <= 16#FF#;
+B_INT <= 2#1010_1010#;
+MONEY := 1_000_000.0;
+FACTOR := 2.2E-6;
+constant DEL1 :time := 10 ns;
+constant DEL2 :time := 2.27 us;
+type MY_LOGIC is ('X','0','1','Z');
+type T_STATE is (IDLE, READ, END_CYC);
+signal CLK : MY_LOGIC := '0';
+signal STATE : T_STATE := IDLE;
+constant FLAG :bit_vector(0 to 7) := "11111111";
+constant MSG : string := "Hello";
+BIT_8_BUS <= B"1111_1111";
+BIT_9_BUS <= O"353";
+BIT_16_BUS <= X"AA55";
+constant TWO_LINE_MSG : string := "Hello" & CR & "World";</code></pre>
+
+<h2>Full example</h2>
+<pre><code>-- example code from: http://www.csee.umbc.edu/portal/help/VHDL/samples/samples.html
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity fadd is -- full adder stage, interface
+ port(a : in std_logic;
+ b : in std_logic;
+ cin : in std_logic;
+ s : out std_logic;
+ cout : out std_logic);
+end entity fadd;
+
+architecture circuits of fadd is -- full adder stage, body
+begin -- circuits of fadd
+ s <= a xor b xor cin after 1 ns;
+ cout <= (a and b) or (a and cin) or (b and cin) after 1 ns;
+end architecture circuits; -- of fadd
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+entity add32 is -- simple 32 bit ripple carry adder
+ port(a : in std_logic_vector(31 downto 0);
+ b : in std_logic_vector(31 downto 0);
+ cin : in std_logic;
+ sum : out std_logic_vector(31 downto 0);
+ cout : out std_logic);
+end entity add32;
+
+architecture circuits of add32 is
+ signal c : std_logic_vector(0 to 30); -- internal carry signals
+begin -- circuits of add32
+ a0: entity WORK.fadd port map(a(0), b(0), cin, sum(0), c(0));
+ stage: for I in 1 to 30 generate
+ as: entity WORK.fadd port map(a(I), b(I), c(I-1) , sum(I), c(I));
+ end generate stage;
+ a31: entity WORK.fadd port map(a(31), b(31), c(30) , sum(31), cout);
+end architecture circuits; -- of add32
+
+use STD.textio.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_textio.all;
+
+entity signal_trace is
+end signal_trace;
+
+architecture circuits of signal_trace is
+ signal a: std_logic_vector(31 downto 0) := x"00000000";
+ signal b: std_logic_vector(31 downto 0) := x"FFFFFFFF";
+ signal cin: std_logic := '1';
+ signal cout: std_logic;
+ signal sum: std_logic_vector(31 downto 0);
+begin -- circuits of signal_trace
+ adder: entity WORK.add32 port map(a, b, cin, sum, cout); -- parallel circuit
+
+ prtsum: process (sum)
+ variable my_line : LINE;
+ alias swrite is write [line, string, side, width] ;
+ begin
+ swrite(my_line, "sum=");
+ write(my_line, sum);
+ swrite(my_line, ", at=");
+ write(my_line, now);
+ writeline(output, my_line);
+ end process prtsum;
+
+end architecture circuits; -- of signal_trace</code></pre>