Hash :
c1657499
Author :
Date :
2014-04-22T11:26:18
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#ifndef A1_COMMON_H
#define A1_COMMON_H
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
/********** work queue */
struct work_ent {
struct work *work;
struct list_head head;
};
struct work_queue {
int num_elems;
struct list_head head;
};
/********** chip and chain context structures */
/* the WRITE_JOB command is the largest (2 bytes command, 56 bytes payload) */
#define WRITE_JOB_LENGTH 58
#define MAX_CHAIN_LENGTH 64
/*
* For commands to traverse the chain, we need to issue dummy writes to
* keep SPI clock running. To reach the last chip in the chain, we need to
* write the command, followed by chain-length words to pass it through the
* chain and another chain-length words to get the ACK back to host
*/
#define MAX_CMD_LENGTH (WRITE_JOB_LENGTH + MAX_CHAIN_LENGTH * 2 * 2)
struct A1_chip {
int num_cores;
int last_queued_id;
struct work *work[4];
/* stats */
int hw_errors;
int stales;
int nonces_found;
int nonce_ranges_done;
/* systime in ms when chip was disabled */
int cooldown_begin;
/* number of consecutive failures to access the chip */
int fail_count;
/* mark chip disabled, do not try to re-enable it */
bool disabled;
};
struct A1_chain {
int chain_id;
struct cgpu_info *cgpu;
struct mcp4x *trimpot;
int num_chips;
int num_cores;
int num_active_chips;
int chain_skew;
uint8_t spi_tx[MAX_CMD_LENGTH];
uint8_t spi_rx[MAX_CMD_LENGTH];
struct spi_ctx *spi_ctx;
struct A1_chip *chips;
pthread_mutex_t lock;
struct work_queue active_wq;
uint8_t temp;
int last_temp_time;
};
#define MAX_CHAINS_PER_BOARD 2
struct A1_board {
int board_id;
int num_chains;
struct A1_chain *chain[MAX_CHAINS_PER_BOARD];
};
/********** config paramters */
struct A1_config_options {
int ref_clk_khz;
int sys_clk_khz;
int spi_clk_khz;
/* limit chip chain to this number of chips (testing only) */
int override_chip_num;
int wiper;
};
/* global configuration instance */
extern struct A1_config_options A1_config_options;
#endif /* A1_COMMON_H */