IABSD.fr/xenocara/lib/mesa/src/intel/compiler/brw_ir.h

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• Author : jsg
  Date : 2025-06-05 14:17:56
  Hash : 452696b8
  Message : Merge Mesa 25.0.7

• lib/mesa/src/intel/compiler/brw_ir.h

• /* -*- c++ -*- */
  /*
   * Copyright © 2010-2016 Intel Corporation
   *
   * Permission is hereby granted, free of charge, to any person obtaining a
   * copy of this software and associated documentation files (the "Software"),
   * to deal in the Software without restriction, including without limitation
   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   * and/or sell copies of the Software, and to permit persons to whom the
   * Software is furnished to do so, subject to the following conditions:
   *
   * The above copyright notice and this permission notice (including the next
   * paragraph) shall be included in all copies or substantial portions of the
   * Software.
   *
   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
   * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
   * IN THE SOFTWARE.
   */
  
  #pragma once
  
  #include <assert.h>
  #include "brw_reg.h"
  #include "compiler/glsl/list.h"
  
  #define MAX_SAMPLER_MESSAGE_SIZE 11
  
  /* The sampler can return a vec5 when sampling with sparse residency. In
   * SIMD32, each component takes up 4 GRFs, so we need to allow up to size-20
   * VGRFs to hold the result.
   */
  #define MAX_VGRF_SIZE(devinfo) ((devinfo)->ver >= 20 ? 40 : 20)
  
  struct bblock_t;