kmx.io/prism.js/components/prism-verilog.js

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components/prism-verilog.js

Branch - branch -master

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Log

Author	Commit	Date	CI	Message
	43124129	2021-12-18T12:49:52		Verilog: Use standard tokens correctly (#3261)
	e2630d89	2021-09-26T11:52:18		ESLint: Added `regexp/sort-alternatives` rule (#3093)
	79d22182	2021-06-08T13:50:35		FIxed some cases of quadratic worst-case runtime (#2922)
	e644178b	2020-12-28T18:19:11		Added test for polynomial backtracking (#2597)
	5d658471	2018-03-08T22:21:24		Code style
	1b24b34b	2017-10-22T15:32:06		Verilog: Regexp simplification
	8aa2cc4a	2017-05-08T13:56:50		Replace [\w\W] with [\s\S] and [0-9] with \d in regexes (#1107) * Replace [\w\W] with [^] and [0-9] with \d in regexes * Replace [\s\S] with [^] * Replace [^] with [\s\S]
	7549eccb	2017-02-08T23:23:24		Add missing greedy config in APL, AutoIt, Dart, Elixir, Erlang, F#, Go, Haxe, Icon, Inform7, J, Makefile, Mel, Nim, Nix, NSIS, OCaml, Oz, Pari/GP, Parser, Pascal, Perl, Prolog, Pure, Qore, R, Rip, Ruby, Rust, SAS, Scheme, SQL, Stylus, Tcl and Verilog
	795eb996	2015-09-16T08:22:27		Verilog: Rename to "Verilog", optimize string regexp, don't use captures unless needed
	1cf50060	2015-07-12T16:41:33		requested changes and personal modifications